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一种用于数字电源的改进型延迟环ADC设计 被引量:1

Design of an Improved Delay-ring ADC Used in Digital SMPS
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摘要 针对用于数字控制DC/DC变换器中模数转换器(ADC)的特点,提出了一种改进型的延迟环ADC。该ADC工作在低电源电压下,输入电压范围为0.8~1.42 V,5位二进制编码输出高电位为1.2 V,电压转换精度为20 mV/LSB,采样频率最高可达50 MHz。电路工作有两种控制方式可选,一是外加频率为50 MHz的脉冲信号,一是外接1.2 V的电源电压进入自循环状态。最后,在SMIC 0.13μm CMOS 1.2 V工艺下对电路进行了仿真和版图设计,仿真结果表明达到了预期的设计要求。 Based on analog to digital converter(ADC) used in digitally controlled DC/DC converter,this paper proposes an improved delay-ring ADC which works on low-voltage power supply.The new architecture has an input voltage range of 0.8~1.42 V,and 5 bit binary output with 1.2 V high logic level.The voltage conversion pricision is 20 mV/LSB,and the sample frequency is up to 50 MHz.There are two work modes can be settled,one is connecting to im-pulse signal with 50 MHz sample frequency,the other is connecting to 1.2 V power supply and entering into self-cy-cling mode.At last,the complete design is simulated and implemented in SMIC 0.13 μm CMOS 1.2 V process,and it turns out that the simulated results reaches the expectation.
机构地区 东南大学
出处 《电力电子技术》 CSCD 北大核心 2010年第12期44-46,共3页 Power Electronics
基金 国家核高基重大专项资助项目(2009ZX01031-003-003)~~
关键词 数字电源 模数转换器 延迟环 digital power supply analog to digital converter delay-ring
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参考文献5

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二级参考文献6

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