HT模型矢量生成的硬件电路设计与实现

Hardware Design and Implementation of Vector Generation Based on HT Model

为提高高速互连电路中串扰的测试速率,减少IC测试人员的分析和研究时间,降低测试成本;在对半跳变(Half transition,HT)模型进行深入研究的基础上,得出HT模型矢量跳变的规律,并依此设计了HT模型矢量生成电路;该设计采用Verilog HDL语言对HT故障模型矢量进行RTL级建模,在CycloneII器件(EP2C8T144C8)完成了电路实现,并用安捷伦逻辑分析采集实验数据进行实际验证;仿真和验证表明,该设计有效地生成多互连线系统HT模型测试矢量,适用于串扰故障的测试分析和研究。

To improve the speed of interconnect crosstalk test rate,reduce the analysis and research time of the IC testers,reduce cost of test,this paper discusses the Half transition fault model and detailed the law of vector generation based on HT fault model,and to achieve a circuit to efficiently generate HT test patterns.A RTL level model based on verilog HDL language is constructed,in the CycloneII the device（EP2C8T144C8） completed the circuit and collected experimental data for the actual validation based on Agilent logic analyzer.As displayed in the results of simulation and verification,The design is effective for multi-line system interconnect test vectors generation of HT fault model,and provides a basis for corsstalk test analysis research.