超低功耗10bit逐次逼近模数转换器

An Ultra-low power 10-bit SAR ADC

本文研究设计了一种基于CMOS 0.18um工艺下的30uw超低功耗10bit逐次逼近模数转换器(SAR ADC)。本结构为在1.2V低电源电压条件下使用全差分结构,使用1V作为参考电平,经前仿SNR有55.8dB。两个完全对称的电容阵列接入带自校准的比较器,比较器再接入存储器中。为了提高逐次逼近模数转换器的精度、匹配度以及减小整个电容面积,电容阵列采用了与以往传统结构不同的分级电容的方式,所有单元电容都使用相同大小样式的电容。芯片采用Chartered 0.18um工艺实现,并对芯片进行了测试。

This paper presents a 30uw ultra-low power 10 bit successive approximation register（SAR） ADC which is realized in a 0.18um CMOS process.The design uses a fully-differential mode which is under 1.2V source supply,and 1V is used as reference voltage,the SNR of pre-simulation is 55.8dB.The two fully-symmetry capacitor-arraies are combined to the auto-zeroed comparator which is combined to the register.To improve the resolution,matching case,and reduce the whole capacitor area,one kind of new capacitor-array which is different from the classical ones is used,and all of the unit capacitors use the same size and shape.The design was implemented in Chartered 0.18um technology,and the test of the chip was fulfilled.