数字钟的设计

Digital Clock Design

数字钟是由晶体管振荡器电路产生多谐振荡,经过分频器分频后输出稳定的秒脉冲,作为时间基准.秒计数器满60向分计数器进位,分计数器满60向时计数器进位,时计数器以24为一个周期.计数器的输出经译码器送到显示器,可将时、分、秒在相应位置正确显示.计时出现误差或者调整时间时可以用校时电路进行时、分的调整,并实现整点报时功能.

The digital clock is judged by the stable second pulse which is as a time benchmark. And second pulse is spirted by the frequency divider through the transistor muhivibrator. When the second counter over sixty, it will turn to minute counter. When the minute counter over sixty, it will turn to hour counter. Twenty - four is a period of the hour counter. Finally, the output of the counter which can be hours, minutes and seconds will be displayed correctly by the monitor in the corresponding position through the decoder. Rectify time circuit can be used to regulate the error of the counter or the redressal of time. Then the function of chiming on every hour can he also realized.