嵌入式DSP访问片外SDRAM的低功耗设计研究

Research on the low power design of embedded DSP accessing external SDRAM

为了降低DSP外部SDRAM存储系统的功耗，针对DSP访问片外SDRAM的功耗来源特点，提出了基于总线利用率动态监测的读写归并方案。该方案动态监测外部存储器接口（EMIF）总线的利用率，根据总线利用率的不同选择开放的页策略、封闭的页策略或休眠模式；设计了简化的指令Cache（I—Cache），采用块读的方法取指令；设计了写后数据缓冲区．由EMIF对同一行的读写进行归并。经计算，根据EMIF总线利用率的不同（10％～40％），该方案相比单纯采用开放的页策略．功耗可减少5％-20％左右。

To reduce the power consumption of DSP（Digital Signal Processor） external SDRAM system,considering the power source of DSP accessing external SDRAM,this paper proposed the precept of write/read merging based on monitoring bus utilization dynamically.The precept monitored the EMIF （External Memory Interface） bus utilization dynamically,and open-page policy,close-page policy or power down policy is adopted on the basis of bus utilization.Simple instruction-cache was designed,and instructions were fetched by block;write post buffer was designed,and EMIF merged the read/write operations of the same row.Calculations show that the power consumption can be reduced by 5% to 20% than the open-page policy ,when the bus utilization varies from 10% to 40%.