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A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer
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摘要 A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step. A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.
作者 陈奇辉 秦亚杰 陆波 洪志良
机构地区 State Key Laboratory of ASIC and System Fudan University
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第1期90-96,共7页 半导体学报（英文版）
基金 Project supported by the National High Technology Research and Development Program of China(No.2009AA011607) the State Key Laboratory of China
关键词 analog-to-digital converter pipeline SHA removing OPAMP on-chip reference buffer analog-to-digital converter pipeline SHA removing opamp on-chip reference buffer
分类号 TN432 [电子电信—微电子学与固体电子学] TN86 [电子电信—信息与通信工程]
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参考文献11

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Journal of Semiconductors
2011年 第1期

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