期刊文献+

片上网络流量模型的研究与实现

The Study and Implementation on Traffic Model of Network-on-Chip
下载PDF
导出
摘要 分析了三种具有代表性的流量模型:均匀分布、泊松分布、自相似流量模型,并实现了基于这些模型的流量生成器.模拟结果与预期结果符合,目前流量生成器已经应用到实际模拟平台之中. This paper analyzes three representative traffic models frequently used in the network,and implements a traffic generator based on these models.The results of simulation are approximately in line with the expected results and the traffic generator are used in the actual simulation platform right now.
作者 彭元喜 陈诚
出处 《微电子学与计算机》 CSCD 北大核心 2011年第1期161-164,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(60676010) 国家"八六三"计划项目(2007AA01Z108) 教育部长江学者和创新团队发展计划
关键词 流量模型 片上网络 片上多核系统 traffic model networks-on-chip(NoC) chip multiprocessor(CMP)
  • 相关文献

参考文献6

  • 1Benini L, De Mieheli G. Networks on chips: a new SoC paradigm [J]. IEEEComputer, 2002, 35(1): 70-78.
  • 2丁帅,吴宁,葛芬,王祺.片上网络路由单元的系统级建模研究[J].微电子学与计算机,2009,26(1):93-96. 被引量:10
  • 3Arjun S, Dally W J, Gupta A K, et al. GOAL:a load --balanced adaptive routing algorithm for torus net- works[C]//Proceedings of the International Symposium on Computer Architecture (ISCA). USA: San Diego, 2003:194--205.
  • 4Abru P, Beitch D Wavelet. Analysis of long-range- dependent traffic[J]. IEEE Transactions on Information Theory, 1998, 44(1):2-15.
  • 5Leland W E, Taqqu M S, Willinger W, et al. On the self--similar nature of ethernet traffic [J], IEEE/ACM Trans. on Networking, 1994, 2(1) :1-15.
  • 6朱红雷,彭元喜,马卓,尹亚明.一种支持QoS片上网络路由器的设计与实现[J].微电子学与计算机,2010,27(3):136-139. 被引量:1

二级参考文献12

  • 1荆元利,樊晓桠,张盛兵,高德远,周昔平.基于片上网络的系统芯片测试研究(英文)[J].微电子学与计算机,2004,21(6):154-159. 被引量:4
  • 2魏建军,康继昌,雷艳静.NOC的平衡设计[J].微电子学与计算机,2007,24(5):54-57. 被引量:11
  • 3Rijpkema E, C, oossens K, Radulescu A, et al. Trade - offs in the design of a router with both guaranteed and best - effort services for networks on chip[ C]//Design Automation and Test in Europe. Germany, Messe Munich, 2003: 350 - 355.
  • 4Grecu C, Ivanov A, Partha Pande, et al. Toward open Network- on - chip benchmarks [ C ]//First International Symposium on Networks - on - Chip. Princeton, New Jersey, USA, 2007:205 - 212.
  • 5Banerjee A, Mullins R, Moore S. A power and energy exploration of Network- on - Chip architectures[ C]//First International Symposium on Networks- on - Chip. Princeton, USA, New Jersey, 2007..163-172.
  • 6Mullins R, West A, Moore S. Low - latency virtual - channel routers for on - chip networks[ C]//Proceedings of the 31st Annual International Symposium on Computer Architecture. Germany: Munchen, 2004:188 - 197.
  • 7Benini L, Micheli G D. Networks on chips: a new SoC paradigm [J]. IEEE Computer, 2002, 35(1) :70- 78.
  • 8Gossens K, Dielissen J, A Radulescu. E-thereal network on chip: concepts, architectures, and implementations[J]. IEEE Design & Test of Computers, 2005, 22(5) : 414 - 421.
  • 9Kavaldjiev N K. A run - time reconfigurable network - on -chip for streaming DSP applications[D]. University of Twente, Faculty of Electrical Engineering, Mathematics & Computer Science, 2007.
  • 10McKeown N. The iSLIP scheduling algorithm for inputqueued switches [J ]. IEEE/ACM Transactions on Networking, 1999,7(2) : 188 - 201.

共引文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部