摘要
提出了一种SOILDMOS大信号等效电路模型,并给出了功率增益和输入阻抗表达式.基于制备的深亚微米SOI射频LDMOS,测试了功率增益和功率附加效率.深入研究了SOILDMOS功率特性与栅长,单指宽度,工作电压和频率之间关系.栅长由0.5μm减到0.35μm时,小信号功率增益增加44%,功率附加效率峰值增加9%.单指宽度由20μm增加到40μm,600μm/0.5μm器件小信号功率增益降低23%,功率附加效率峰值降低9.3%.漏端电压由3V增加到5V,600μm/0.35μm器件小信号功率增益增加13%,功率附加效率峰值增加5.5%.频率由2.5GHz提高到3.0GHz,射频功率SOILDMOS小信号功率增益降低15%,功率附加效率峰值降低4.5%.
A large signal equivalent circuit model of SOI LDMOS is proposed. Power gain and power-added efficiency of n-type LDMOS are modeled. Deep sub-micron SOI LDMOS was fabricated and measured. We investigated the dependence of SOI LDMOS power characteristics on channel length,single gate finger width,supply voltage and working frequency. Power gain and power-added efficiency are increased by 44% and 9% ,respectively,with channel length reduction from 0. 5 μm to 0. 35 μm. When single gate finger width is increased from 20 μm to 40 μm,power gain and power-added efficiency of 600 μm /0. 5 μm device are decreased by 23% and 9. 3% ,respectively. Power-gain and power-added efficiency are increased by 13% and 5. 5% ,respectively,with supply voltage increased from 3 V to 5 V. When the working frequency is increased from 2. 5 GHz to 3. 0 GHz,power gain and power added efficiency of LDMOS are decreased by 15% and 4. 5% ,respectively.
出处
《物理学报》
SCIE
EI
CAS
CSCD
北大核心
2011年第1期772-777,共6页
Acta Physica Sinica
基金
国家重点基础研究发展计划(批准号:2006CB3027-01)资助的课题~~