12bit 10MS/s流水线结构模数转换器

12 bit 10 MS/s Pipelined Analog-to-Digital Converters

介绍了12 bit,10 MS/s流水线结构的模数转换器IP核设计。为了实现低功耗,在采样电容和运放逐级缩减的基础上,电路设计中还采用了没有传统前端采样保持放大器的第一级流水线结构,并且采用了运放共享技术。瞬态噪声的仿真结果表明,在10 MHz采样率和295 kHz输入信号频率下,由该方法设计的ADC可以达到92.56 dB的无杂散动态范围,72.97 dB的信号噪声失调比,相当于11.83个有效位数,并且在5 V供电电压下的功耗仅为44.5 mW。

A 12 bit 10 MS/s pipelined analog-to-digital converter （ADC） IP core was described. To reduce the power consumption, besides that the sampling capacitors and operational amplifiers were scaled down along pipelined stages, the first pipeline stage was designed without using a conventional front-end sample-and-hold amplifier （SHA）, and operational amplifier sharing technique was also employed. The transient noise simulation results show that the proposed ADC achieves 92.56 dB spurious free dynamic range （SFDR） , 72.97 dB signal-to-noise and distortion ratio or 11.83 effective number of bits （ENOB） for an input frequency of 295 kHz at 10 MHz sampling rate , while consuming only 44.5 mW at 5 V supply voltage.