基于FPGA的CCSDS图像数据压缩系统的设计

Design of CCSDS image compression system based on FPGA

针对CCSDS图像数据压缩(IDC)标准,提出了一种基于FPGA的CCSDS IDC并行实现方案.该方案包括离散小波变换(DWT)、直流系数量化编码、位平面编码(BPE)、码字拼接等4个模块.位平面编码模块采用了并行扫描、并行编码的快速算法,以提高编码速度.仿真结果表明了本方案的可行性和有效性,处理时间比现有的CCSDS IDC串行编码改进方法减少了13.6%,适用于空间通信的图像数据压缩编码.

We report the design and implementation of CCSDS image data compression（IDC） parallel scheme based on FPGA.This scheme includes four modules：discrete wavelet transform（DWT）,direct coefficient quantified encoding,bit plane encoding（BPE）,and code processing.In order to put on speed,we use the parallel scanning and parallel encoding in the BPE module.The experimental results show the feasibility and efficiency of this scheme,and compared to the modified method of CCSDS IDC serial encoding,the processing time has reduced by 13.6%.Our scheme is fit for image data compression in the space communication.