一种流水线ADC级间增益非线性误差的数字域补偿方法

Digital Calibration of Interstage Gain Nonlinearity in Pipelined ADC

基于流水线ADC(模数转换器)结构中级间残差放大器的增益压缩特性,合理地将其建模为奇数次幂级数形式,详细描述并分析确定了它产生的非线性失真对ADC性能的影响方式与权重.针对性地提出了数字域反向抵消方案,通过引入数字伪随机序列的方式,利用二阶统计互相关的信息自适应地辨识与逼近实际模型系数,并采用此估计值在后台实现级间增益非线性补偿过程.对14位三级流水线ADC进行系统模拟,当前两级量化精度为5位,且两级残差放大器的输出峰值点的相对增益压缩率均为5%时,经过补偿后,SFDR(无杂散失真动态范围)和SNDR(信噪失真比)指标分别从67.84dB、51.26dB提高到94.16dB、72.97dB.该方法为高精度流水线ADC的设计提供了可供参考的结论和技术解决方案.

According to the gain compression mechanism,interstage residue amplifiers of pipelined ADC（Analog to Digital Converter） would generally cause nonlinear distortions,which could be reasonably modeled as odd-order power series.Effect and weight of the interstage gain nonlinearity on the overall quantization accuracy are defined and characterize.A digital background calibration technique is then proposed for post nonlinearity correction using estimated coefficient of the model,which would be adaptively identified employing second-order cross-correlation information with digital pseudo-random sequence added into the signal path.Simulations are performed for a 14-bit Pipelined ADC with three stages.Assuming the first two 5-bit stages both have third-order nonlinearity corresponding to a gain compression of 5% at full scale,results show that with this calibration scheme,SFDR and SNDR are improved from 67.84dB、51.26dB to 94.16dB、72.97dB respectively high-resolution pipelined ADC designs would benefit much from the error analysis conclusion and technical solution proposed in the paper.