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降低协同设计虚拟机启动开销的译码后指令缓存技术 被引量:3

Decoded Instruction Cache for Reducing Startup Overhead in Co-Designed Virtual Machines
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摘要 协同设计虚拟机采用动态二进制翻译实现不同体系结构间的二进制兼容,对源指令的翻译和处理影响了协同设计虚拟机的启动性能.研究发现,在一个采用解释执行和翻译相结合的协同设计虚拟机中,处理非热点代码的解释执行是虚拟机启动开销的主要来源.发现了协同设计虚拟机中的解释例程局部性,并提出了一种硬件译码后指令缓存结构DICache(decoded instruction cache),用于存储解释执行过程中译码后的指令信息,开发解释例程的局部性,避免大量重复的译码操作.在一个协同设计虚拟机上对DICache进行评估,采用一组SYSmark 2004 SE商业应用测试程序进行测试.结果表明,DICache可以有效减少重复译码量,将协同设计虚拟机的启动性能平均提高约2.4倍.与相关的优化技术相比,DICache的性能更好,且具有更强的适用性. Co-designed virtual machines(co-VM) provide the processor designer with new opportunities for innovation through the combined hardware and software.Co-VM uses dynamic binary translation to implement binary compatibility between different instruction set architectures(ISA).Interpreting and translating the source ISA binaries will affect the startup performance of a co-VM.In the exploration of startup performance of our VM which employs interpretation and superblock translation,we observe that the cold code interpretation causes the major startup overhead of co-VM and the redundant source instruction decoding forms the bottleneck of interpretation.We oberserve the interpretation routine locality and propose a hardware decoded instruction cache(DICache) for saving instruction information decoded during interpretation.DICache can be organized as normal cache and maintained by hardware.We implement a co-VM and conduct some benchmarks from SYSmark 2004 SE to evaluate the DICache performance on a co-VM.We also evaluate the implementation overhead of DICache,such as area and power consumption.It is demonstrated that DICache could significantly reduce the redecoding operations and speedup the interpretation,thus bringing a speedup of 2.4 on average relative to the startup performance of the normal co-VM.Compared with other related optimization techniques,DICache performs more efficiently with better adaptability.
出处 《计算机研究与发展》 EI CSCD 北大核心 2011年第1期19-27,共9页 Journal of Computer Research and Development
基金 国家"九七三"重点基础研究发展计划基金项目(2007CB310901) 国家自然科学基金项目(60803041) 国家"八六三"高技术研究发展计划基金项目(2009AA01Z101)
关键词 协同设计 虚拟机 动态二进制翻译 解释执行 启动开销 co-design virtual machine dynamic binary translation interpretation startup overhead
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参考文献12

  • 1Smith J E, Nair R. Virtual Machines: Versatile Platforms for Sysetms and Processes [M]. Beijing: Publishing House of Electronics Industry, 2006.
  • 2Dehnert J C, Grant B K, Banning J P, et al. The transmeta code MorphingTM software: Using speculation, recovery, and adaptive retranslation to address real-life challenges [C] //Proc of the 1st Annual IEEE/ACM Int Symp on Code Generation and Optimization (CGO'03). Washington, DC: IEEE Computer Society, 2003: 15-24.
  • 3Ebcioglu K, Altman E R. DAISY: Dynamic compilation for 100% architectural compatibility [C]//Proc of 24th lnt Syrup on Computer Architecture (ISCA'97). New York: ACM, 1997:26-37.
  • 4马湘宁,武成岗,唐锋,冯晓兵,张兆庆.二进制翻译中的标志位优化技术[J].计算机研究与发展,2005,42(2):329-337. 被引量:9
  • 5Hwu W W, Mahlke S A, Chen W Y, et aI. The superblock: An effective technique for VLIW and superscalar compilation [J]. Journal of Supereomputing, 1993, 7(1/2):229-248.
  • 6Hu S, Smith J E. Reducing startup time in co-designed virtual machines [C] //Proc of the 33rd Annual Int Symp on Computer Architecture (ISCA'06). Washington, DC: IEEE Computer Society, 2006:277-288.
  • 7SimpleScalar LLC. SimpleScalar 3.0 [OL]. [2009-09-19]. http ://www. simplescalar, com.
  • 8Bochs 2. 3. 6 [OL]. [2009-09-19]. http://sourceforge, net/ projects/bochs/files/bochs/2. 3. 6/boehs-2. 3. 6/.
  • 9Business Applications Performance Corporation (BAPCO). An overview of SYSmark 2004 SE [OL]. [2009-08-16]. http://www, bapco, corn/support/technical documents/SYSmark 2004 SEWhitePaper. pdf.
  • 10HP Corporation. CACTI 4.0[OL]. [2009-09-19]. http:// quid. hpl. hp. com: 9081/cacti/.

二级参考文献12

  • 1E. R. Altman, D. Kaeli, Y. Sheffer. Welcome to the opportunities of binary translation. IEEE Computer, 2000, 33 (3): 40~45.
  • 2M. Srinivasan. Method and apparatus for emulating status flag.USA, US Patent 5774694, 1998.
  • 3R.J. Hookway, M. A. Herdeg. Digital FX! 32: Combining emulation and binary translation. Digital Technical Journal, 1977,9(1): 3~12.
  • 4P. Hohensee, M. Myszewski, D. Reese. WABI CPU emulation.Hot Chips Ⅷ, Palo Alto, CA, 1996.
  • 5C. Cifuentes, M. Van Emmerik. UQBT: Adaptable binary translation at low cost. IEEE Computer, 2000, 33(3): 60~66.
  • 6A. Klaiber. The technology behind Crusoe processor. Transmeta Corporation, Tech Rep, 2000.
  • 7243190 Intel Architecture Software Developer's Manual,Volume 1: Basic Architecture. Santa Clara: Intel Corporation,1999.
  • 8243191 Intel Architecture Software Developer's Manual,Volume 2: Instruction Set Reference. Santa Clara: Intel Corporation, 1999.
  • 994039-7311 MIPS R4000 Microprocessor User's Manual (Second edition). Mountain View: MIPS Technologies Inc, 1994.
  • 10A.V. Aho, R. Sethi, J. D. Ullman. Compilers: Principles,Techniques, and Tools. Beijing: Post & Telecommunications Press, 2001.

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