基于移位多项式基优化并行RS伴随式计算电路的方法

Optimal design of Reed-Solomon parallel syndrome computation with shifted polynomial basis

研究了RS译码器的并行伴随式计算电路的结构优化,分别推导了并行度能整除和不能整除码长时的并行伴随式计算的表达式,并设计了相应的电路。针对并行实现会增加电路复杂度的问题,通过适当的变换,采用移位多项式基的方法,设计了低复杂度的并行伴随式计算改进电路。改进结构不仅降低了电路中有限域加法器的复杂度,并且通过将原有的多个小规模有限域乘法器简化为一个较大规模的乘法器,使得乘法器的复杂度也在很大程度上得到了降低。对并行度为8的RS(2040,2024)和RS(255,239)译码器的实验研究表明,上述的结构实现方法可比迭代匹配算法(IMA)节省约30%的资源,当并行度为64时,资源节省可达到50%。

The research on optimization of Reed-Solomon （RS） parallel syndrome computation was conducted. The expressions for parallel syndrome computation when the codeword length is and is not exactly divided by the parallel factor were derived, and their corresponding circuits were designed. In consideration of the circuit complexity increment caused by the parallel design, an improved parallel syndrome computation architecture with the reduced complexity was proposed by transforming the syndrome expression properly and representing the production of the multiplier, in the shifted polynomial basis. In this architecture, the complexity of the multiplications is reduced by removing the multipliers in the inputs of the adders, and the complexity of the additions is diminished by decreasing the overlapped basis. The experimental resuhs show that the hardware complexity can be reduced by 40% in the design of the RS（2040,2024） and RS（255,239） codes with the parallel factor of 8, and the hardware complexity can be reduced by 64% in the design of the RS（2040, 2024） codes with the parallel factor of 64.