深亚微米芯片设计的研究

A Study on the Design of Deep Submicron Chips

为了满足深亚微米芯片的高速性能,一方面要精确地定位电路各部分的延迟模型,另一方面必须把实际布图后互连延迟信息返标到逻辑综合环境。研究了深亚微米芯片设计中的时序模型、线网的线负载模型及EDA工具上的实现过程。

There is a need for more accurate and elaborate delay models in designing deep submicron chips Investigations are made into the delay model,the wire load model for wire net and the synthesis process on EDA tools for the design of deep submicron chips