摘要
选取具有对称系数的生成多项式,利用Top-down设计方法设计并用CPLD实现了RS(255,223)码编码器。该编码器可装入一片Flex8000系列EPF8820ATC144-2芯片中,所用逻辑单元数为537个(该芯片共有627逻辑单元),约8700个门,可稳定工作在10MHz频率上。与已有的相同设计相比。
A VLSI RS(255,223) encoder with symmetric coefficients of generator polynomial is presented The encoder is designed using top down design method and implemented in an EPF8820ATC144 2 CPLD chip,in which 537 logic cells are used,and there are about 8700 gates It operates steadily above 10 MHz Compared to encoders with indentical design,this encoder has a better tradeoff between speed and area
出处
《微电子学》
CAS
CSCD
北大核心
1999年第5期347-350,共4页
Microelectronics
