针对FPGA优化的高分辨率时间数字转换阵列电路

An FPGA-optimized high resolution time-to-digital converter array

介绍一种针对FPGA优化的时间数字转换阵列电路。利用FPGA片上锁相环对全局时钟进行倍频与移相,通过时钟状态译码的方法解决了FPGA中延迟的不确定性问题,完成时间数字转换的功能。在Altera公司的FPGA上验证表明,本时间数字转换阵列可达1.73 ns的时间分辨率。转换阵列具有占用资源少,可重用性高,可以作为IP核方便地移植到其他设计中。

An FPGA-optimized high resolution time-to-digital converter array is proposed. In this design, we adapt the onchip PLL as the frequency double circuit and the clock phase shifter. We use the method of clock state decoding to solve the delay uncertainty for FPGA, thereby fulfill the time to digital convert. The circuit has been implemented via FPGA produced by Altera Corp. The result shows that the time resolution is 1.73 ns. It enjoys the advantages of less resource usage, high reusability and easy implantation as IP cores.