三维叠层DRAM封装中硅通孔开路缺陷的模拟(英文)

Modeling TSV Open Defects in 3D-Stacked DRAM

采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道。然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战。通过大量的模拟研究,本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效测试和诊断这种缺陷方法的第一步。

Three-dimensional（3D） stacking using through silicon vias（TSVs） is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors.The large number of TSVs implemented in 3D DRAM circuits,however,are prone to open defects and coupling noises,leading to new test challenges.Through extensive simulation studies,this paper models the faulty behavior of TSV open defects occurred on the wordlines and the bitlines of 3D DRAM circuits,which serves as the first step for efficient and effective test and diagnosis solutions for such defects.