摘要
提出了一种新颖的CMOS四象限模拟乘法器电路,该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0.18μm CMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1.8 V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0.3 V,-3 dB带宽可达到1 GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。
A novel four-quadrant analog multiplier circuit based on a cross-coupled squarer topology combining with subtraction circuits is presented. The circuit is implemented in 0. 18μm technique of CMOS. The results of HSPICE simulation show that the proposed multiplier has a statiic-state power dissipation of 80μw, its linear range with respect to both differential input voltages is 0.3 V and its bandwidth is about 1 GHz when it works at 1.8 V. Under the same power consumption and power voltage level, the proposed multiplier shows better linearity comparing with previous low power multiplier.
出处
《现代电子技术》
2011年第2期139-141,144,共4页
Modern Electronics Technique
基金
2007年姑苏创新创业领军人才项目(ZXG0719)
关键词
CMOS模拟乘法器
低压
高线性
减法电路
CMOS analog multiplier
low-voltage
high-linearity
subtraction circuit
