高速数字接收机中位同步与滤波联合实现方法

A Joint Implementation for Bit Synchronization and Filtering in High-Speed Digital Receivers

针对高速数字接收机中的位同步问题,提出了一种位同步与滤波联合实现结构.该结构利用一次快速傅里叶变换(FFT)运算将信号变换至频域,从中提取定时信息并实现定时恢复,同时完成滤波处理,极大地降低了系统的运算量,节约了硬件资源,并且能够先于载波同步稳定工作.理论分析与仿真结果表明,该结构算法复杂度低,比常用时域方法减少了约60%的运算量,能够在中等信噪比条件下(15 dB以上)准确实现位同步,适用于高速调制解调系统.

To deal with the problem of timing recovery in high-speed digital receivers,a joint implementation for bit synchronization and filtering is presented,which converts the signal to the frequency domain through the tool of fast Fourier transform（FFT）.Therefore,the scheme could greatly depress not only the algorithm complexity but also the cost of hardware resources.In addition,the module could work stably prior to carrier synchronization.Both theory analysis and computer simulation show that this architecture has a low computational complexity,and could achieve the timing recovery accurately under a normal signal-to-noise condition（about 15 dB）.Also there is probably 60% decrease of the computation in contrast to the arithmetic working in time domain.The presented module could be adapted to the high-speed demodulator.