摘要
在数字通信中,为保证信息传输和交换的正确,各种数字模块的时钟应该具有相同的频率,否则在数据传输中会产生滑动、误码,直至通信中断。本文详细论述了基于FPGA技术实现数据码流位同步时钟信号的提取,以及电路模块的工作原理、关键技术和实现途径,并通过了软件仿真。
To ensure data transmission and exchange correctly in digital communication,clocks for various digital modules should have the same frequency,otherwise,sliding,error code will occur in data transmission until communication interruption.Extraction of implementing data code flow bit synchronization clock signal based on FPGA（Field-programmble Gate Array）,and operation principle of circuit modules,key techniques and implementation approach are addressed in detail,and all of these are simulated with software.
出处
《火控雷达技术》
2010年第4期91-95,共5页
Fire Control Radar Technology
关键词
数字锁相环
位同步时钟
异或门鉴相器
digital phase-locked loop
bit synchronization clock
XOR phase detector
