摘要
针对大容量现场可编程门阵列(FPGA)时间数字转换电路线性度较差的问题,采用小容量FPGA实现了用于激光测距的高精度、高线性度时间数字转换电路。通过对高速计数器、数字插入方法、编码器硬件算法的研究,分析了影响时间数字转换电路精度和非线性误差的因素,提出了一种降低非线性误差的方法。首先,根据所分析的影响因素,解决了高速锁存的问题,在单片小容量FGPA XC2V250上实现了时间数字转换电路;接着,通过USB接口将携带时间信息的计数器值和温度计码转为二进制编码值传给PC机,进行计算和显示;最后,设计了延时测量电路,对所设计的时间数字转换电路进行了测试,得到了各个延时单元延时的大小,并进行了数据分析和处理。测试结果显示:时间数字转换电路单次测时分辨率约为80 ps,校正后可达40 ps左右,微分非线性误差为-0.524LSB^+0.448LSB,积分非线性误差为-1.598LSB^+1.492LSB,可以满足飞行时间法激光测距中高精度测时的要求。
A low-density Field Programmble Gate Array(FPGA) was chosen to realize a high-accuracy,low nonlinearity Time-to-Digital Converter(TDC) circuit to a laser range finder,for the high-density FPGA TDC circuit showed a worst linearity.The high-speed counter,interpolator methods and the encoder algorithm were studied,and the factors effecting on the high-resolution and nonlinearity of TDC circuit implemented in a single FPGA were analyzed.Then,a method to reduce the nonlinearity of TDC circuit was proposed.Focusing on the method,a high-speed latch problem was settled based on the above factors,and a TDC circuit was designed by a low-density FPGA XC2V250.A USB interface was used to transfer the time signal into the digital code to a PC to be calculated and displayed.Finally,a time measurement circuit was designed to measure the delay time of TDC delay cells.Obtained delay time was processed and analyzed,and experimental results indicate that the single plot precision of the TDC circuit is about 80 ps,and the time interval resolution after calibration can reach 40 ps.The differential nonlinearity and integral nonlinearity of TDC circuit are between-0.524LSB and +0.448LSB,-1.598LSB and +1.492LSB,respectively.
出处
《光学精密工程》
EI
CAS
CSCD
北大核心
2010年第12期2665-2671,共7页
Optics and Precision Engineering
基金
中国科学院光电技术研究所预研资助项目
关键词
激光测距
时间数字转换电路
FPGA
非线性度
laser range finder
Time-to-Digital Converter(TDC)
Field programmble Gate Array(FPGA)
nonlinearity