数字电视条件接收系统的加扰算法芯片设计

Scrambling Algorithm Chip Design of Digital TV Conditional Access System

简要介绍了DVB数字视频广播条件接收系统中通用加扰算法的原理。基于Altera公司StratixⅡ系列的FPGA,底层各模块采用硬件描述语言(Verilog HDL)进行描述,顶层采用原理图设计的方式,设计出采用DVB通用加扰算法的加扰器。利用Quar-tus Ⅱ7.2进行编译、仿真,从对编译及各模块的仿真结果分析,块加密模块与流加密模块的最高时钟频率分别达到229.89MHz与331.27MHz,达到了设计要求。最后在FPGA上测试表明:本设计可以应用于实际TS流的加扰。

The theory of the common scrambling algorithm in DVB conditional access system is described. Based on Altera Stratix II FPGA, the Common Scramhting Algorithm is designed,with hardware description language （Verilog HDL） in the bottom of the module and schematic design in the top-level. From the analysis of the simulation resuh of cach module,the design meets the design requirements after compilation and simulation by Quartus II 7.2. The maximum clock frequency of the block cipher and the stream cipher are 229. 89 and 331.27 MHz, respectively. Finally,the test indicates in a FPGA chip that the design can be applied to scramble of the actual TS stream.