OFDM系统中低存储可配置的(Ⅰ)FFT的设计与实现

Design and Implementation of reduced-Memory and reconfigurable(Ⅰ)FFT processor for OFDM system

文章提出了一种OFDM系统中高速、可配置、低存储的(Ⅰ)FFT处理器设计方法。该方法采用了按频率抽取的基4流水线结构实现高速运算,利用单个原位同址运算RAM及CORDIC算法实现低存储运算,通过改变流水线的级数实现多种点数的(Ⅰ)FFT运算。整个设计通过FPGA实现。在外部时钟为100 MHz时,处理器计算一次4096点、13位长数据FFT的时间约为103μs,所消耗的存储器仅为106 Kb。

This paper proposes a high speed,reduced-memory and reconfigurable(I)FFT processor for OFDM systems.the processor uses radix-4 DIF pipeline architecture for high speed computation.In order to meet the low memory requirement,single in-place memory and CORDIC algorithm are adopted.Implemented on a FPGA device,the processor can calculate a 4096-point complex FFT in 103us when operates at 100MHz,while just consumes 106KB memory.