基于FPGA的数字锁相环设计

Design of Digital Phase Locked Loop Based on FPGA

简要介绍异或门数字锁相环的工作原理和组成部分,并且分析了各模块参数选择对数字锁相环纹波的影响。文章针对于此,设计出一种最佳匹配参数下的数字锁相环,在FPGA平台上用Verilog HDL语言实现硬件电路,整个系统具有快速锁定,纹波最小以及精度高等优点。

The composing and principle of XOR-Digital Phase Locked Loop are simply described.And every module＇s parameters based on the ripple of DPLL are analyzed.A DPLL with best parameters match is introduced,which is achieved with Verilog language on FPGA platform.The quality of system appears quick latching,minimum ripple and high precision.