摘要
对一个针对数字下变频应用的抽取滤波器从设计指标到版图实现的设计过程进行了详细介绍。该抽取滤波器实现了20倍的降采样,由CIC滤波器、CIC补偿滤波器和半带滤波器三级依次串联而成。通过利用抽取滤波器的等价变换和多项分解性质,各滤波器级的硬件电路开销和运行功耗都得到了降低。
Design of a decimation filter for digital down-conversion was presented in detail.The decimation filter,which was implemented by successively cascading a CIC filter,a CIC compensation filter and a half-band filter,achieved a decimation factor of 20.By utilizing equivalent transformation and polyphase decomposition of the decimation filter,both hardware cost and operating power of each sub-decimation filter were also reduced.
出处
《微电子学》
CAS
CSCD
北大核心
2011年第1期1-5,共5页
Microelectronics
基金
国家自然科学基金资助项目(60906009)
