摘要
为减少在静止无功补偿(SVC)装置中晶闸管的触发误差,设计了一种基于FPGA(现场可编程门阵列)的全数字锁相环(ADPLL),并进行硬件电路测试。同时分析了全数字锁相环的各模块工作原理并进行了参数设计和电路仿真。最后在实验平台上进行了测试。结果显示,该环路可稳定跟踪电网信号,可为SVC数字控制系统提供快速、稳定、高精度的同步信号。
In order to reduce the thyristor triggering error in the static var compensator(SVC),all digital phase-locked loop(ADPLL) is designed based on field programmable gate array(FPGA).Principle of each module is analyzed,and the parameter design and the circuit simulation are completed.Finally,it is tested on experimental platform.The result shows that the ADPLL can stably track power network signal.It provides fast,stable and accurate synchronized signal for the SVC numerical control system.
出处
《电力系统及其自动化学报》
CSCD
北大核心
2011年第1期103-107,共5页
Proceedings of the CSU-EPSA
关键词
全数字锁相环
静止无功补偿装置
触发误差
现场可编程门阵列
同步信号
all digital phase locked loop(ADPLL)
static var compensator(SVC)
triggering error
field programmable gate array(FPGA)
synchronized signal