期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity 被引量：9

Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity
原文传递
导出
摘要 A low power mapping algorithm for technology independent AND/XOR circuits is proposed. In this algorithm, the average power of the static mixed-polarity Reed-Muller （MPRM） circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes, and the power and area of MPRM circuits are estimated by using gates from a given library. On the basis of obtaining an optimal power MPRM circuit, the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed-Muller circuits and AND/OR circuits, power saving is up to 44.22% and 60.09%, and area saving is up to 14.13% and 32.72%, respectively. A low power mapping algorithm for technology independent AND/XOR circuits is proposed. In this algorithm, the average power of the static mixed-polarity Reed-Muller （MPRM） circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes, and the power and area of MPRM circuits are estimated by using gates from a given library. On the basis of obtaining an optimal power MPRM circuit, the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed-Muller circuits and AND/OR circuits, power saving is up to 44.22% and 60.09%, and area saving is up to 14.13% and 32.72%, respectively.
作者 汪鹏君 李辉
机构地区 Institute of Circuits and Systems
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第2期108-113,共6页 半导体学报（英文版）
基金 Project supported by the National Natural Science Foundation of China(Nos.61076032,60776022) the Postdoctoral Science Foundation of China(No.20090461355) the Postdoctoral Research Projects of Zhejiang Province,China,and the Natural Science Foundation of Zhejiang Province,China(No.Y1101078)
关键词 AND/XOR circuits low power mapping MPRM polarity optimization AND/XOR circuits low power mapping MPRM polarity optimization
分类号 TN702 [电子电信—电路与系统]
  • 相关文献

参考文献14

  • 1Roy K, Prasad S C. Low-power CMOS VLSI circuit design. Canada: Simultaneously, 2000.
  • 2Sasao T. Easily testable realizations for generalized Reed-Muller expressions. Transactions on Computers, 1997, 46(6): 709.
  • 3Wang P, Lu J, Chen K, et al. Low power polarity conversion based on the whole annealing genetic algorithm. Journal of Semi- conductors, 2008, 29(2): 298.
  • 4A1 Jassani B A, Urquhart N, Almaini A E A. Manipulation and optimisation techniques for Boolean logic. Computers and Digi- tal Techniques, 2010, 4(3): 227.
  • 5Buyuksahin K M, Najm F N. Early power estimation for VLSI circuits. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(7): 1076.
  • 6Tsui C Y, Pendram M, Despain A M. Technology decomposition and mapping targeting low power dissipation. Design Automa- tion Conference, 1993: 68.
  • 7Zhou H, Wong D F. Exact gate decomposition algorithm for low-power technology mapping. International Conference on Computer-Aided Design, Digest of Technical Papers, 1997:575.
  • 8Narayanan U, Liu C L. Low power logic synthesis for XOR based circuits. International Conference on Computer-Aided Design, Digest of Technical Papers, 1997:570.
  • 9Zhou H, Wong D F. Optimal low power XOR gate decomposi- tion. Design Automation Conference, 2000:104.
  • 10A1 Jassani B A, Urquhart N, Almaini A E A. Minimization of in- completely specified mixed polarity Reed Muller functions using genetic algorithm. International Conference on Signals, Circuits and Systems, 2009:1.

同被引文献64

  • 1万旭,唐金花,陈偕雄.基于K图的逻辑函数OC展开式在固定极性下的化简[J].浙江大学学报（理学版）,2006,33(1):48-51. 被引量：3
  • 2Yang Meng,A.E.A. Almaini,Wang Pengjun.FPGA PLACEMENT OPTIMIZATION BY TWO-STEP UNIFIED GENETIC ALGORITHM AND SIMULATED ANNEALING ALGORITHM[J].Journal of Electronics(China),2006,23(4):632-636. 被引量：6
  • 3Tan E C, Yang H. Optimization of fixed-polarity Reed- Muller circuits using dual-polarity property [J]. Circuits, Systems, and Signal Processing, 2000, 19(6): 535-548.
  • 4Habib M K. Efficient and fast algorithm to generate minimal Reed-Muller exclusive-OR expansions with mixed polarity for completely and incompletely specified functions and its computer implementation [J]. Computers & Electrical Engineering, 1993, 19(3):193-211.
  • 5Habib M K. A new approach to generate fixed-polarity Reed- Muller expansions for completely and incompletely specified functions [J]. International Journal of Electronics, 2002, 89 (11) : 845-876.
  • 6Rahaman H, Das D K, Bhattacharya B B. Testable design of AND-EXOR logic networks with universal test sets [J]. Computers & Electrical Engineering, 2009, 35(5):644-658.
  • 7Wang L, Almaini A E A. Optimisation of Reed-Muller PLA implementations [J]. IEE Proceedings Circuits, Devices and Systems, 2002, 149(2): 119-128.
  • 8Dill K M, Perkowski M A. Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with generalized Reed-Muller (AND-EXOR) forms [J]. Journal of Systems Architecture, 2001, 47(6): 477-489.
  • 9A1Jassani B A, Urquhart N, Almaini A E A. Manipulation and optimisation techniques for Boolean logic[J]. IET Computers & Digital Techniques, 2010, 4(3): 227-239.
  • 10Wang L, Almaini A E A. Exact minimisation of largemultiple output FPRM functions [J].IEE Proceedings Computers and Digital Techniques, 2002, 149(5): 203-212.

引证文献9

二级引证文献24

Journal of Semiconductors
2011年 第2期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部