外延CeO_2高k栅介质层的结构及介电性能

Structure and dielectric properties of epitaxial CeO_2 thin films for high-k gate dielectric layer

利用脉冲激光沉积两步生长法在Si(111)衬底上制备了厚度为10～40 nm的外延CeO2薄膜,构建了Pt/CeO2/Si MOS结构,研究了CeO2薄膜的界面及介电性能。实验发现,界面处存在的电荷对MOS结构C-V特性的测量有较大影响,采用两步生长法制备的外延CeO2薄膜在保持较大介电常数的同时有效降低了界面态密度。由等效氧化物厚度-物理厚度曲线得出CeO2薄膜的介电常数为37;根据Hill-Coleman法计算出CeO2薄膜界面态密度为1012量级。

Epitaxial CeO2 thin films, 10-40 nm thick, were deposited on Si（lll） substrate by the pulsed laser deposition two-step method. The metal-oxide-semiconductor（MOS） structures were further fabricated to evaluate the interface and dielectric properties of CeO2 films. The results show that the C-V characteristics can be greatly affected by the interface charges. The epitaxial CeO2 thin films, which are deposited by two-step process, possess larger permittivities and lower interface state density. The permittivity calculated from the EOT-/phys characteristics curve is 37, and according to Hill-Coleman method, the interface state density is 10^12 order of magnitude.