基于CPLD的高速脉冲信号采集系统设计

Design of High Speed Pulse Sampling System Based on CPLD

介绍了一种基于CPLD(复杂可编程逻辑器件)的高速脉冲信号采集系统的设计与实现方案。该系统最大的特点是对离散脉冲信号的幅值进行采样,采样过程完全由CPLD控制,无需CPU干预。采用VHDL语言与模块化的设计思想设计了A/D采集控制模块、数据存储控制模块、微处理器接口模块,实现了多个串行ADC的同步脉冲采样与数据的实时存储。实验结果验证了系统的正确性,该系统与微处理器的接口灵活方便,也可用于一般的连续信号采样,具有一定的通用性和工程应用价值。

A CPLD-based design for high-speed pulse sampling system is described.The characteristic of the system is to sample the discrete pulse amplitude,and the sampling process is totally controlled by the CPLD,without CPU controls.VHDL language and the modular programming method are adopted in this system,three modes are designed by the programmer,induding A/D acquisition mode,data storage mode and CPU interface mode.Multi-serial ADC simultaneous sampling and real-time data saving are realized.The experiment results show that the design is rational,as well as the CPU interface is flexible.The system can also be used to sample continuous signal and has a certain extent practicality value.