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基于半动态电路的32位高性能加法器设计

Design of High-Performance 32 bit Adder with Semi-Dynamic Circuit
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摘要 描述了一种采用半动态电路的32位高性能加法器的设计.设计中改进了现有稀疏树结构中的输出进位逻辑,在此基础上,设计了一种容偏斜多米诺和静态电路相结合的半动态电路,以及相应的多个控制时钟的时序策略.根据几种不同的加法器负载驱动情况,分别设计出不同的电路尺寸.采用SMIC 1.8V0.18μm CMOS工艺,在不同条件下的仿真结果表明,加法器电路取得了良好的性能. This paper presents a programme of designing 32 bit high-performance adder with semi-dynamic circuit.With modified output carry logic in sparse-tree structure,the semi-dynamic adder circuit,which includes skew-tolerant dynamic domino-circuit and static circuit,and its multiple clocks timing scheme were designed.The different transistor＇s sizes of adder were designed to fit the different loads and drive conditions of the adder.In SMIC 1.8 V 0.18 μm technology,the simulation results under different conditions show that the designed adder has a high performance.
作者 刘志哲 仲顺安 袁家芬
机构地区 北京理工大学信息与电子学院
出处 《北京理工大学学报》 EI CAS CSCD 北大核心 2011年第2期191-195,共5页 Transactions of Beijing Institute of Technology
关键词 加法器 稀疏树 半动态电路 多米诺 adder sparse-tree semi-dynamic domino
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献9

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北京理工大学学报
2011年 第2期

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