高层次综合中的可测性模块分配方案

Testability-Oriented Module Allocation Method in High Level Synthesis

高层次综合中的模块分配会直接影响到寄存器分配方案,进而影响到综合后电路的面积、时延、功耗和可测性.为此提出一种面向可测性的模块分配方案.在讨论了考虑可测性的模块分配原则之后,提出面向可测性的模块分配的权重图模型,并在此基础上给出基于权重图的可测性模块分配算法.按照最大可测性提高的原则,通过动态地修改权重对模块进行考虑可测性的均衡分配,并最终输出模块分配方案.对标准电路进行实验的结果表明,除了较小的面积开销外,采用文中方案的电路的可测性优于其他方案.

Module allocation in high level synthesis can influence register allocation scheme directly, and affect area, time delay, power consumption and testability as a result. So a testability-oriented module allocation method is given. After the module allocation rules which take the testability into consideration are given, a testability-oriented weighted graph model for module allocation is presented. Then the weighted graph based module allocation algorithm for improving testability is obtained. According to the biggest testability improvement rule, balanced module allocation scheme is given by modifying the weight dynamically. Experiments on benchmarks show that the algorithm in this paper gives a better testability than other schemes with less area overhead.