摘要
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
基金
Project supported by the SDC Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)
the AM Foundation Project of Science and Technology Commission of Shanghai Municipality (Grant No.08700741000)
the Leading Academic Discipline Project of Shanghai Education Commission (Grant No.J50104)
the Innovation Foundation Project of Shanghai University
