摘要
介绍了自主研制的200 V/40 A VDMOS晶体管的设计优化过程及研制结果。该器件采用JFET注入和浅P-body方法降低导通电阻,提高电流密度,采用优化的N掺杂硅外延材料优化导通电阻和击穿电压。测试结果表明击穿电压高于215 V,特征导通电阻1.2Ω.mm2,导通电流可达40 A;同时设计了ESD防护,HBM值7.5 kV;芯片总面积小于31.25 mm2,可采用TO220封装。
A 200 V/40 A VDMOSFET has been developed.The device introduces a means of JFET implantation and shallow P-body to reduce on-resistance,increase current density,so that to reduce the chip area,and uses n-type silicon epitaxial material to optimize Ron and blocking voltage.The test result indicates that the blocking voltage is above 215 V,the special on-resistance is 1.2 Ω·mm2,the on state current can be up to 40 A,and the HBM of the ESD protection structure is 7.5 kV.The total area of chip is less than 31.25 mm2,so it can be packaged with the type of TO220.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2011年第1期85-89,共5页
Research & Progress of SSE
基金
广东省省级财政支持技术项目(JGZB2008004)
