一种高性能LDO的缓冲器分析与设计

Analysis and design of a buffer for high performance LDO

为了提高低压差稳压器(LDO)的动态响应性能,提出了一种新型的缓冲器电路。通过引入该缓冲器,LDO的瞬态性能得到显著提高的同时,空载时的静态电流也大大减小。对缓冲器电路的工作原理进行了分析,指出通过降低缓冲器的输出阻抗,扩展了系统的带宽,进而减小了环路的响应时间。指出通过对输出功率管的动态充放电,降低了电路的静态功耗。给出了设计实例,并采用CSMC 0.6μm CMOS工艺模型进行仿真,仿真结果验证了所提出缓冲器的可行性及理论分析的正确性。

A novel buffer circuit of the Low-Dropout（LDO） regulator is presented to improve its transient behavior.By using this buffer,LDO＇s quiescent current in the case of light-load is greatly reduced.The working principle of the buffer circuit is analyzed,and it is pointed out that the system＇s bandwidth is extended by reducing the buffer＇s output impedance.Additionally,it also improves the respond speed of the system and reduces the quiescent power consumption.The simulation results based on the CSMC 0.6 μm CMOS process verify the correctness of the theoretical analysis and the feasibility of the proposed methods.