面向硬件仿真的SystemVerilog断言检查电路生成研究

Checker circuit generation for SystemVerilog assertion in hardware emulation

提出了一种针对SystemVerilog断言的断言检查电路综合方法。综合而成的断言检查电路可以被用于硬件仿真中。方法基于移位寄存器链保存电路信号的历史数据,并利用断言电路间寄存器共用减少硬件资源使用。实验结果表明,与已有的断言综合方法比较,本方法具有有效性。

In this paper,a method to generate hardware checker circuits from SystemVerilog assertions for hardware emulation is proposed.The main idea is to construct the checker circuit based on shift-register chain.It also introduce a method to minimize the hardware resource consumption by sharing registers among different assertions.The experimental results comparing with former the researches show the effectiveness of the proposed method.