摘要
传统分数倍采样率变换方案应用于宽带全数字接收机系统时,部分数字电路处理速率将高达GHz量级,这成为系统数字实现的瓶颈。该文从分数倍采样基本原理出发,通过对升采样与多相滤波器级联响应进行推导分析,得出一种改进的分数倍采样率变换方案,使得高时钟数字电路得以避免。改进方案与传统方案的电路综合结果对比证明了理论分析的正确性。结果表明,改进方案对数字器件处理速率的需求仅为传统方案的1/min{I,D},且不受采样率变换比例I/D的影响,I与D分别为内插倍数与抽取倍数。
The processing speed of some digital circuits reaches GHz level with the conventional scheme of fractional sampling rate transformation used in wideband all digital receivers,which becomes a bottleneck of the digital realization.The cascaded response of the up-sampling process and the poly-phase filter was analyzed based on the fractional sampling rate transformation theory,with an improved transformation scheme then derived.Comparison between the results of the improved scheme and the conventional scheme shows the theoretical analysis validity.The results show that the requirement of the improved scheme on the processing speed of digital devices is only 1/min{I,D} of the conventional scheme with the requirement of the improved scheme being free from I/D,where I and D are interpolation and decimation factors.
出处
《清华大学学报(自然科学版)》
EI
CAS
CSCD
北大核心
2010年第10期1641-1645,共5页
Journal of Tsinghua University(Science and Technology)
基金
国家"八六三"高技术项目(2007AA01Z2b3)
关键词
数字信号处理
分数倍采样
非整数倍采样
采样率变换
多速率
宽带
digital signal processing
fractional sampling
non-integer sampling
sampling rate transformation
multi-rate
wideband