期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于可重构系统的时域划分技术的研究

The Research on the Temporal Partitioning Based on Reconfigurable System
下载PDF
导出
摘要 可重构计算是一种介于ASIC和通用微处理器之间的新的提升计算机性能的方法,对于数字信号处理、流媒体技术、图像压缩、密码学、生物信息处理等计算密集型方面的应用,可重构计算技术可以发挥巨大的优势。基于具有较少重构时间的实时可编程逻辑器件（如FPGA）的用户可编程性,其可作为多种硬件资源使用。如果其配置信息可以迅速更改,则由逻辑器件实现的硬件功能也可实现迅速切换。硬件资源的大小是有限的,那些超过器件有效硬件资源的较大任务需要通过时域划分来解决。该文对可重构计算以及时域划分的定义、分类,国内外研究现状和常见的研究方法做了详细的描述,并综合分析了一系列时域划分算法并进行了相关比较。 Reconfigurable computing is a new method between ASIC and GPP to improve the performance of the computer,which could be used to the application about Digital Signal Processing,the technology of Stream Media,Image Data Compression,Cryptology,Bioinformation and so on.Chips based on runtime programmable logic devices（such as the case of FPGAs——field programmable gate arrays） with low reconfigurable time is programmable by users,so it could be used as various hardware resources.If we could change the reconfiguring information of the devices quickly,the switching of hardware function can be realized by logic devices.As the hardware resource is limited,the large scale task which exceed the available hardware resources should be temporal partitioned.This paper introduces the definition,classification,the research status internal and oversea and some general research methods.We also analyse some of temporal partitioning methods and compare them with each other.
作者 周洲 ZHOU Zhou（Tongji University,Shanghai 201804,China）
机构地区 同济大学
出处 《电脑知识与技术》 2011年第2期910-912,915,共4页 Computer Knowledge and Technology
关键词 时域划分 可重构计算 现场可编程门阵列(FPGAs) 数据流图 temporal partition reconfigurable computing FPGAs DFG
分类号 TP301 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献12

  • 1Estrin G.Parallel Processing in a Restructurable Computer System[J].IEEE Trans.Electronic on Computers,1963,12(5):747-755.
  • 2Bhat N.Novel Techniques for High Performance Field Programmable Logic Devices [D].PhD thesis,Univ, of California, Berkeley, Electronic Reserach Laboratory,UCB/ERL-93-80,1993.
  • 3Long X P,Amano H.WASMII: a Data Driven Computeron a Virtual Hardware [C]//Napa Valley,CA:Proc 1st IEEE Workshop on Field Programmable Custom Computing Machines1993:33-42.
  • 4Cardoso J M P.On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures[J]. IEEE Transaction On Computers,2003,52(11): 1362-1375.
  • 5Cardoso J M P,Neto H C.An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs [C]//Lisbon:IFIP X International Conference on Very Large SCale Integrmion,1999.Silveira L M,Devadas S,Reis R.VLSI:Systems on a Chip, Kluwer Academic Publishers,1999:485-496.
  • 6Hudson R,Lehn D I,Athannas P M.A Run-time Reconfigurable Engine for Image Interpolation[C]//Proceedings of 6th IEEE Symposium on FPGAs for Custom Computing Machines,Napa Valley:IEEE,1998:88-95.
  • 7Purna K M G,Bhatia D.Temporal Partitioning and Scheduling Data Flow GraPhs for Reconfigurable Computers[J].IEEE Transactions on Computers, 1999,48(6):579-590.
  • 8Kaul M,Vemuri R.Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs[C]//Paris,France:Proc. of Design, Automation & Test in Europe,1999:202-209.
  • 9Zhang X J,Ng K W.A Temporal Partitioning Approach Based on Reconfiguration Granularity Estimation for Dynamically Reconfiguration Systems[C]//Proceedings of 2nd IEEE International Conference on Field-Programmable Technology,Tokyo:IEEE,2003:344-347.
  • 10Takayama A,Shlbata Y,Iwal K,et al.Dataflow Partitioning and Scheduling Algorithms for WASMII: A virtual Hardware[C]//Villach, Austria:Proceedings of 10th International Conference on Field-Programmable Logic and Applications,2000:685-694.

二级参考文献13

  • 1[1]COMPTON K,HAUCK S.Reconfigurable computing:a survey of systems and softwareACM Computing Surveys,2002,34(2):171-210.
  • 2[3]DANDALIS A,PRASANNA K.An adaptive cryptographic engine for internet protocol security architecturesACM Transactions on Design Automation of Electronic Systems,2004,9(3):333-353.
  • 3[4]DASU A,PANCHANATHAN S.Reconfigurable media processingElsevier's Parallel Computing,Special Issue on Parallel Computing in Image and Video Processing,2002,28(7/8):1111-1139.
  • 4[5]HUDSON R,LEHN I,ATHANAS M.A run-time reconfigurable engine for image interpolationProceedings of 6th IEEE Symposium on FPGAs for Custom Computing Machines.Napa Valley:IEEE,1998:88-95.
  • 5[6]PURNA G,BHATIA D.Temporal partitioning and scheduling data flow graphs for reconfigurable computersIEEE Transactions on Computers,1999,48(6):579-590.
  • 6[7]KAUL M,VEMURI R,GOVINDARQJAN S,et al.An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applicationsProceedings of the 36th ACM/IEEE Conference on Design Automation.New Orleans:ACM,1999:616-622.
  • 7[8]ZHANG X J,NG K W.A temporal partitioning approach based on reconfiguration granularity estimation for dynamically reconfigurable systems Proceedings of 2nd IEEE International Conference on Field-Programmable Technology.Tokyo:IEEE,2003:344-347.
  • 8[9]TAKAYAMA A,SHLBATA Y,IWAL K,et al.Dataflow partitioning and scheduling algorithms for WASMII,a virtual hardwareProceedings of 10th International Conference on Field-Programmable Logic and Applicaions.Villach:Springer,2000:685-694.
  • 9[10]SELVAKKUMARAN N,KARYPIS G.Multi-objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization Proceedings of 22nd International Conference on Computer Aided Design.San Jose:IEEE,2003:726-733.
  • 10[11]MAHMOUD M,MASATO M.A combined approach to high-level synthesis for dynamically reconfigurable systemsIEEE Transactions on Computers,2004,53(12):1508-1522.

共引文献6

电脑知识与技术
2011年 第2期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部