一种电子系统认证芯片的电源规划

Power Planning of Electronic System Certification Chip

为了对所开发的电子产品进行保护,采用ASIC的方法设计基于硬加密技术的电子系统认证芯片。在后端物理设计中,为了使最终的芯片实现面积优化且满足功耗、时序等要求,采用预设计的方法对芯片进行功耗预估与布线拥塞分析。根据分析结果提高了芯片利用率,并针对预设计中存在的电压降(IR Drop)违规进行了详细的电源规划,包括全局电源网络的连接、电源环和电源条的设计,最终满足了功耗要求,实现了时序收敛以及面积优化。

The electronic system certification chip based on the hardware encryption technology is designed with the design method of ASIC to protect the electronic products. The power consumption estimation and routing congestion analysis of the chip are performed with the method of pre-design to achive the area optimization, and meet the requirements of power con sumption and time sequence during the physical design. According to the analysis results, the chip utilization ratio is improved and the detailed power planning is designed to fix 1R drop violations existing in the pre design. The requirements of the power consumption, time-sequence convergence and area optimization are satisfied.