基于FPGA的一种新型数字鉴频鉴相器的设计

A Digital PFD Design for Phase-locked Loop Control Based on FPGA

对于电机的锁相控制,需要对相差进行PI性质的环路滤波,但现有的锁相环中鉴频鉴相器输出为相差脉冲而非数字量,难以直接进行PI特性的环路滤波。该文提出了一种基于FPGA的新型数字鉴频鉴相器,通过对晶振时钟的非整数分频获取准确的参考时钟,基于触发器计数机制实现了PFD相差脉冲的数字量化,且可以输出频差数字量。利用VHDL硬件描述语言进行设计,在ModelSim软件中进行仿真,并在EPF10K40型FPGA芯片中进行综合实现,仿真和实验结果验证了该方法的正确性和有效性,为电机锁相控制中环路滤波参数的调整及控制算法的改进提供了便利条件。

A PI loop filter is needed for PLL control of motor,but the normal PFD has an output of phase error pulse instead of numeric digitals in phase-locked loop,which makes it hard to design a PI loop filter using pulse output.This paper proposed a novel digital phase-frequency detector based on FPGA.Numeric output of phase and frequency error was realized based on flip-flop counter mechanism and a precise reference clock was achieved with method of a non-integer division of crystal clock.VHDL hardware description language was used to design the modules,and ModelSim was introduced to implement logic and sequential simulation.An experiment was carried on in Altera EPF10K40 chip.Both the simulation and experimental results verify the correctness and validity of the method,which greatly enhance the convenience of adjustment of parameters and improvement of control algorithms.