小尺寸器件栅隧穿电流预测模型

Gate Tunneling Current Predicting Model for Scaled Devices

针对具有超薄氧化层的MOS器件,使用积分方法,提出了一个新的栅隧穿电流与氧化层厚度关系的理论预测模型,在此基础上使用HSPICE对MOS器件的特性进行了详细的研究,并定量分析了器件的工作情况,预测了在栅隧穿电流的影响下小尺寸器件的特性变化趋势。使用BSIM 4模型进行仿真的结果与所提出的理论模型相符合。

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel gate tunneling current predicting model using integral means is presented for ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of sealed MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using H-Simulation program with integrated circuit emphasis （HSPICE） simulator. The simulation results in BSIM 4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.