多码率QC-LDPC译码器设计与实现

Design and Implementation of Multi-rate QC-LDPC Decoder

低密度奇偶校验码(LDPC)是目前最有效的差错控制手段之一,而其中准循环LDPC码(QC-LDPC)应用最为广泛。提出了一种通用的多码率QC-LDPC译码器设计方法,并在FPGA上完成了实现和测试。测试结果表明,该多码率译码器在资源占用不超过2种码率译码器资源之和的前提下能够有效支持至少3种码率;且工作时钟在110 MHZ时,固定迭代次数为16次,该译码器的吞吐率能保持在110 Mb/s以上。

Low-density parity-check（LDPC） code is one of the most effective error-controlling methods,in which the quasi-cyclic（QC） LDPC code is the most popular class.This paper proposes a design method for multi-rate QC-LDPC decoder,and then describes the implementation and test on FPGA.The test results show that the resource occupied by the multi-rate decoder is not more than two times of the resource occupied by the single-rate decoder,and this multi-rate decoder could support at least 3 code rates with the throughput higher than 100Mbps when the iteration number is fixed to 16 and the clock frequency set to 110 MHz.