重模多项式乘法在FPGA上的实现

Implementation of double-module polynomial multiplication on FPGA

为降低基于重模多项式剩余类环矩阵的密码算法中乘法运算占用的硬件资源量,提出了一种剩余类环上乘法的流水线实现方法.该方法选用数模为216,多项式模为4次首一多项式的重模多项式剩余类环,对流水线设计进行了数学推导,给出了重模多项式剩余类环上可综合乘法模块和不可综合测试模块的Verilog HDL代码,并利用ModelSim软件进行仿真测试.测试结果表明,此方法不仅能够提高乘法运算的速度,而且将16位乘法器的数目从28个降到8个,大大降低了硬件资源消耗量,使得重模多项式剩余类环上矩阵乘法在一般的硬件电路中得以实现,为该类密码算法的推广和应用奠定了基础.

To reduce the hardware consumption,a pipe-line method is proposed to implement the multiplication in double-module polynomial residue ring.The method chooses 216 as integer module and any quartic polynomial with the leading coefficient to be one as polynomial module.The pipe-line method is designed according to mathematical derivation.The synthesizable multiplication module and the test module which is unsynthesizable are compiled by Verilog HDL.Finally,the pipe-line method is simulated on ModelSim.The test results show that the new method not only speeds up the multiplication,but also makes the number of 16-bit multiplier decrease from 28 down to 8.Significant reduction of hardware resource consumption ensures that multiplication of double-module polynomial matrix can be realized in a normal circuit.So,it is of great significance to the promotion and application of encryption algorithm based on double-module polynomial residue ring.