一种基于CPLD高速大容量双端口RAM电路系统的设计

A Design of Circuit System Based on CPLD in Dual-Port RAM

双端口RAM在智能仪器高速数据采集中扮演着重要的作用.提出了一种高速、大容量、低成本的双端口随机存储器(RAM)的设计方案,该方案通过对复杂可编程(CPLD)进行逻辑电路设计实现.仿真结果表明,双端口RAM的读写控制时序完全符合双端口RAM的时序要求,读写结果正确.解决了目前市场上缺少高速、大容量、低成本的双端口RAM的问题,方便高速数据采集与处理仪器的快速开发.

Dual-port RAM plays an important role in intelligent instrument of high-speed data acquisition. The scheme and the circuit of dual-port RAM, which are high in speed, large in volume and low in cost, are introduced in this paper. The approach was adopted by programming logic circuit in complicated programmable logic device （CPLD）. The simulation result of dual-port RAM is verified correct in the timing, the outcome of reading operation and writing operation. The design, which helps the quick development of data sampling and processing instrument, solves the shortage of high-speed, large-volume and low-cost dual-port RAM.