用二维坐标下降法实现x=b/a的FPGA设计

FPGA Design of the Dichotomous Coordinate Descent Algorithm for Complex Divider Problems

以二维坐标下降法(DCD算法)为基础,每次成功迭代后以二分之一的步长进行下一次迭代,使得它在解决线性方程时不仅保证了收敛度,并且实现了在FPGA(现场可编程门阵列)中无需用乘法器就可以计算出两个参数的比率,最后通过Matlab仿真验证了DCD算法在此应用中的可行性及其收敛速度快的特点.

Based on the dichotomous coordinate descent（DCD） algorithm,having the next iteration with the power of half step size after a successful iteration guarantees the convergence speed when it solves the problem with the linear equations.It makes it possible to get the ratio of two numbers without multiplication on FPGA.MATLAB simulation is carried out to verify that the DCD algorithm has higher convergence speed in the application.