CMOS低噪声放大器Miller效应分析与噪声优化

Miller effect analysis and noise optimization of CMOS low noise amplifier

根据反馈分解理论将晶体管栅漏电容分解等效到放大器输入输出两端,研究了栅漏电容对低噪声放大器(LNA)输入阻抗和噪声系数的影响.基于分析结果对阻抗及噪声公式进行了修正,提出功耗约束条件下的LNA噪声优化方法.设计的2.4GHz LNA基于中芯国际(SMIC)0.18μm RF CMOS工艺,版图后仿结果表明:在1.2V的工作电压下,该低噪声放大器直流功耗仅为2.4mW,噪声系数为1.0dB,功率增益为16.3dB,输入输出反射损耗均小于-22dB,三阶互调点IIP3为-3.2dBm.相比已有的设计,根据修正公式设计的LNA在功耗、输入阻抗匹配、噪声系数等性能指标上有较大的改善.

According to feedback decomposition theorem（FDT）,the gate-drain capacitance of a transistor was decomposed into the input and output nodes.Then the influence of gate-drain capacitance on input impedance and noise figure of low noise amplifier（LNA） were discussed.Based on the analytic result,revised input matching and noise figure formulas were developed,also the noise optimization method under the constraint of power dissipation was proposed.The post-layout simulation results show that the 2.4 GHz LNA,based on SMIC 0.18 μm RF CMOS（Complementary Metal Oxide Semiconductor） technology,consumes a low DC power of 2.4 mW from a 1.2 V supply,noise figure of 1.0 dB,power gain of 16.3dB,input and output losses below-22 dB,and input third-order intercept point of-3.2 dBm.Compared with existing designs,the proposed 2.4 GHz LNA based on the revised formulas had lower power dissipation,better input impedance matching and lower noise factor.