基于高速缓存资源共享的TLB设计方法

Translation look-aside buffer design method based on cache resource reusing

针对嵌入式处理器中旁路转换缓冲(TLB)功耗和面积显著的问题,提出一种共享高速缓存硬件资源的低功耗TLB设计方法,消除了传统方法中TLB存储器的硬件资源及静态功耗.该方法通过设立两级TLB低功耗架构和缓存地址映射表,有效减少TLB的访问次数,降低了功耗;利用高速缓存的结构特性动态扩展TLB表项,扩大对物理内存的映射范围,提升TLB命中率.进一步提出了一种复用缓存替换策略的TLB表项的编码加锁方法,减少页面抖动,缓和TLB表项与指令、数据的资源冲突.实验结果表明:与传统的TLB设计相比,应用本方法的嵌入式处理器的功耗下降28.11%,面积减少21.58%.

A new translation look-aside buffer（TLB） design method with cache resource reusing was proposed for reducing the power consumption and area cost in the embedded processor.This method bases on a two-level TLB architecture and an address mapping table of cache,and decreases the frequency of TLB accesses with low power consumption.The dynamic expansion mechanism of TLB entry with cache resource reusing enlarges the mapping range of physical address for high TLB hit rate.Moreover,a locking method of TLB entry was proposed to balance the resource hazard between TLB entry and instruction/data in cache.Comparing with the traditional TLB design,experiments showed that the proposed method reduced the power consumption and the area cost of embedded processor by 28.11% and 21.58% respectively.