基于历史链接关系的指令高速缓存低功耗方法

Linking history based low-power instruction cache

针对现代嵌入式处理器中指令高速缓存功耗显著的问题,提出一种基于Cache行间访问历史链接关系的指令高速缓存低功耗方法.通过创建独立可配置的顺序及跳转链接表项,利用链接表项中缓存的历史信息,消除Cache行间访问时对标志位存储器和冗余路数据存储器的访问功耗.进一步提出可复用的链接状态单元,克服了传统方法中由于缓存缺失引起的清空和重建链接表项的缺陷,显著降低了指令高速缓存访问功耗.实验表明,与传统指令高速缓存相比,本方法在取指单元面积仅增加1.35%的情况下,可平均减少标志位存储器访问次数96.38%.

A low power instruction cache accessing method based on inter-line linking history was proposed to reduce the power dissipation of instruction cache,which is more significant in modern embedded processor.By creating configurable sequential and jumping linking table（SJLT）,this method eliminates the inter-line accessing power of tag and redundant data memory.Moreover,a reusable linking status unit（LSU） is also created to solve the linking table flush and reconstruction problem caused by cache miss in the traditional methods.Utilizing both SJLT and LSU effectively,significant reduction on dynamic power consumption was successfully achieved.Experimental results showed that,in comparison with the traditional instruction cache,the novel method reduced 96.38% of the tag access with only 1.35% area increment of instruction fetch unit.