基于多晶外基区及SIC技术的高速NPN管设计

Design of High-Speed NPN Transistor Based on Poly-Silicon-Base and SIC Technology

提出了一种先进的双多晶硅非自对准NPN管的器件结构,并实际用于一种高性能NPN管的研制。该器件结构主要通过多晶外基区减小基区电阻和基区结面积,以及使用SIC技术减小集电极电阻的方式,极大地提升了NPN管的特征频率。通过实际工艺流片验证,实现了BVCEO=5.6 V、fT=13.5 GHz的高速NPN管。该器件结构较双多晶自对准器件结构易于加工,可以广泛用于其他高速互补双极器件的研制。

An advanced double poly-silicon non-self-aligned（DPNSA） structure of NPN device was proposed and experimentally demonstrated with a high performance NPN transistor.In the structure,poly-silicon base was used to reduce base resistance and base-junction area,and selectively implanted collector（SIC） was employed to reduce collector resistance,which significantly improved cut-off frequency（fT） of NPN device.Finally,NPN transistor with BVCEO of about 5.6 V and fT of about 13.5 GHz was fabricated.The novel structure is easier to fabricate,compared to double poly-silicon self-aligned structure,and so it can be used for high-speed complementary bipolar device.