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适用于MPEG2视频解码的VLD设计 被引量:2

A VLSI Structure of Variable Length Decoder Compatible with MPEG2 Standard
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摘要 提出了一种新的适用于MPEG2 视频解码的变字长解码(VLD)结构,根据MPEG2 变字长码表的特点,通过合理的码字分割解决码字的存储问题,采用桶式移位器,使得每个时钟能处理一个码字。由于比特流中最长的码长为24 比特,故采用32 位的内部总线结构,减小了电路规模。用1.0 μm CMOS单元库进行综合,在50MHz时钟频率下工作时电路规模为6000 A novel architecture for Variable Length Decoding(VLD) algorithm for MPEG2 video decoder is proposed in the paper According to the characteristics of MPEG2 DCT coefficients table,the storage of codeword is solved by proper codeword partitioning Barrel shift register is used so that each codeword can be processed in one clock period Since the longest codeword is 24 bits,32 bit data bus is used to reduce the scale of circuit The VLD is synthesized with 1 0 μm CMOS cell library,and is implemented in 4000 gates when operating at 50 MHz
出处 《微电子学》 CAS CSCD 北大核心 1999年第6期428-431,共4页 Microelectronics
关键词 视频解码 变字长解码 MPEG2 图像编码 ASIC Video decoding Variable length decoding DCT coefficients MPEG2
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参考文献2

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同被引文献14

  • 1戴春泉,李锦涛,黄晁.适用于H.264视频解码器的VLD设计[J].计算机工程,2005,31(13):162-164. 被引量:4
  • 2薛全,张颖,刘济林,郑伟,李东晓.基于变步长分组的H.264系数码表优化[J].电路与系统学报,2006,11(3):115-117. 被引量:8
  • 3HARI KALVA. The H. 264 video coding standard[J]. IEEE MultiMedia,2006,13(4) :86-90.
  • 4THOMAS WARSAW, MARCIN LUKOWIAK. Architecture design of an H. 264/AVC decoder for real-time FPGA implemen- tation[A]. IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06) [C]. Colorado:Steamboat Springs, 2006 : 253-256.
  • 5MYTHRI ALLE, BISWAS J, NANDY S K. High performance VLSI architecture design for H. 264 CAVLC decoder[A]. IEEE 17th International Conference on Application Specific Systems, Architectures and Processors (ASAI>06)[C]. Colorado: Steamboat Springs, 2006 : 317-322.
  • 6YI-MING LIN,PEI-YIN CHEN. An efficient implementation of CAVLC for H. 264/AVC[A]. First International Conference on Innovative Computing, Information and Control(ICICIO06) [C]. Beijing : 2006 : 601-604.
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