基于FPGA的低杂散直接数字频率合成器设计与实现

A Low-Spurious Direct Digital Frequency Synthesis Based on FPGA

在分析了DDS其杂散来源及已有抑制方法的基础上,提出了一种新的有效抑制杂散的方法,经三角函数变换,将通常被舍掉的相位累加器输出的低B位利用起来。在Simulink中进行了仿真,结果显示在相位累加器位宽为32 bit,查找表寻址位数为12 bit时,较之未经优化的DDS,其杂散改善了60 dB。用Verilog语言设计实现,通过FPGA验证,在示波器中观察到了理想的正弦波输出。

After analyzing the principle of DDS,the causes for its spur and some methods to reduce spurs,a new and effective method of spur-reducing was proposed.Using the trigonometric transformation,the low B-bits which were usually be truncated in the output of phase accumulator were utilized.The results in Simulink appeared that the spurious performance of the optimized DDS was improved to 60 dB,when the phase accumulator is 32 bit and 12 bit wide for look-up table addressing.The DDS was implemented in the FPGA by using the Verilog language as a design input,and finally an ideal sine wave was observed by oscilloscope.